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KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
CMOS DRAM
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
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Fast Page Mode operation Byte/Word Read/Write operation CAS-before-RAS refresh capability RAS-only and Hidden refresh capability Self-refresh capability (L-ver only) Fast parallel test mode capability TTL(5V)/LVTTL(3.3V) compatible inputs and outputs Early Write or output enable controlled write JEDEC Standard pinout Available in Plastic SOJ and TSOP(II) packages Single +5V3/410% power supply (5V product) Single +3.3V3/40.3V power supply (3.3V product)
Part Identification - KM48C2000B/B-L (5V, 4K Ref.) - KM48C2100B/B-L (5V, 2K Ref.) - KM48V2000B/B-L (3.3V, 4K Ref.) - KM48V2100B/B-L (3.3V, 2K Ref.)
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Active Power Dissipation Unit : mW Speed 4K -5 -6 -7 324 288 252 3.3V 2K 396 360 324 4K 495 440 385 5V
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2K
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605
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550 495
FUNCTIONAL BLOCK DIAGRAM
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Refresh Cycles Part NO. C2000B V2000B C2100B V2100B VCC 5V 3.3V 5V 3.3V 2K 32ms Refresh cycle 4K Refresh period Normal 64ms 128ms
Refresh Timer Refresh Control Refresh Counter Memory Array 2,097,152 x 8 Cells Row Decoder Sense Amps & I/O RAS CAS W Control Clocks VBB Generator Vcc Vss
L-ver
Data in Buffer
DQ0 to DQ7
U
Performance Range Speed -5 -6 -7
tRAC
50ns 60ns 70ns
tCAC
13ns 15ns 20ns
tRC
90ns 110ns 130ns
tPC
35ns 40ns 45ns
Remark 5V/3.3V 5V/3.3V 5V/3.3V
A0-A11 (A0 - A10)*1 A0 - A8 (A0 - A9)*1
Row Address Buffer Col. Address Buffer Column Decoder
Data out Buffer OE
Note) *1 : 2K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
CMOS DRAM
PIN CONFIGURATION (Top Views)
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KM48C/V20(1)00BK
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KM48C/V20(1)00BS
VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 DQ2 DQ3 W RAS *A11(N.C) A10 A0 A1 A2 A3 VCC
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS DQ7 DQ6 DQ5 DQ4 CAS OE A9 A8 A7 A6 A5 A4 VSS
*A11 is N.C for KM48C/V2100B(5V/3.3V, 2K Ref. product) K : 300mil 28 SOJ S : 300mil 28 TSOP II
Pin Name A0 - A11 A0 - A10 DQ0 - 7 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs (4K Product) Address Inputs (2K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5V) Power(+3.3V) No Connection (2K Ref. product)
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating
CMOS DRAM
Units 5V -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V E W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70E)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3*2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0*2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 V V V V Units
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Input Leakage Current (Any input 0AVINAVIN+0.3V, all other input pins not under test=0 Volt) 3.3V Output Leakage Current (Data out is disabled, 0VAVOUTAVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0AVINAVIN+0.5V, all other input pins not under test=0 Volt) 5V Output Leakage Current (Data out is disabled, 0VAVOUTAVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL II(L) IO(L) VOH VOL Min -5 -5 2.4 -5 -5 2.4 Max 5 5 0.4 5 5 0.4 Units uA uA V V uA uA V V
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM48V2000B ICC1 Don't care Normal L Don't care -5 -6 -7 Don't care -5 -6 -7 -5 -6 -7 Don't care -5 -6 -7 Don't care Don't care 90 80 70 1 1 90 80 70 80 70 60 0.5 0.3 90 80 70 450 250 KM48V2100B 110 100 90 1 1 110 100 90 90 80 70 0.5 0.3 110 100 90 400 250 Max KM48C2000B 90 80 70 2 1 90 80 70 80 70 60 1 0.3 90 80 70 450 300
CMOS DRAM
Units KM48C2100B 110 100 90 2 1 110 100 90 90 80 70 1 0.3 110 100 90 400 300 mA mA mA mA mA mA mA mA mA mA mA mA uA mA mA mA uA uA
ICC2
ICC3
ICC4
Don't care Normal L Don't care L L
ICC5
ICC6 ICC7 ICCS
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V, Din=Don't care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
CAPACITANCE (TA=25E, VCC=5V or 3.3V, f=1MHz)
Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ7] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0EA TAA70E, See note 1,2)
Test condition (5V device) : VCC=5.0V3/410%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition (3.3V device) : VCC=3.3V3/40.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Symbol Min -5 Max Min 110 155 50 13 25 0 0 3 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 13 13 10K 37 25 10K 13 50 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 10K 45 30 10K 15 50 60 15 30 0 0 3 50 70 20 70 20 20 15 5 0 10 0 15 35 0 0 0 15 15 20 20 10K 50 35 10K 20 50 -6 Max Min 130 185 70 20 35 -7 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 4 9 3,4,9 3,4 3,9 3 5 2 Units Notes
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL
90 133
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
AC CHARACTERISTICS (Continued)
Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay time CAS set-up time (CAS -before-RAS refresh) CAS hlod time (CAS -before-RAS refresh) RAS to CAS precharge time CAS precharge time (CBR counter test Access time from CAS precharge Fast Page mode cycle time Fast Page read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -5 Max Min 0 10 32 64 128 0 36 73 48 53 5 10 5 20 30 35 76 10 50 30 13 13 0 13 10 10 10 10 100 90 -50 13 15 0 15 10 10 10 10 100 110 -50 15 200K 40 85 10 60 35 15 20 0 20 10 10 10 10 100 130 -50 200K 0 40 85 55 60 5 10 5 20 35 45 100 10 70 40 32 64 128 0 50 100 65 70 5 15 5 30 -6 Max Min 0 15 -7
CMOS DRAM
Units Max ns ns 32 64 128 ms ms ms ns ns ns ns ns ns ns ns ns 40 ns ns ns ns 200K ns ns 20 ns ns 20 ns ns ns ns ns ns us ns ns
Notes 8 8
tDS tDH tREF tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPT tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS
0 10
6 6 6 6 6
3
5
10 10
12 12 12
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column address to RAS lead time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge to W delay timerefresh) Fast Page mode cycle time Fast Page read-modify-write cycle time RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -5 Max Min 115 160 55 18 30 55 18 18 55 30 41 78 53 58 40 81 55 200K 35 18 18 18 20 20 10K 10K 65 20 20 65 35 45 90 60 65 45 90 65 200K 40 20 25 25 65 20 35 10K 10K 75 25 25 75 40 55 105 70 75 50 105 75 -6 Max Min 135 190 -7
CMOS DRAM
( Note 10, 11 )
Units Max ns ns 75 25 40 10K 10K ms ms ms ns ns ns ns ns ns ns ns ns ns ns 200K 45 25 ns ns ns ns ns 3 6 6 6 6 3,4,9 3,4 3,9 Notes
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tCPWD tPC tPRWC tRASP tCPA tOEA tOED tOEH
95 138
KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol. 6. tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCSAtWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDAtCWD(min), tRWDAtRWD(min), tAWDAtAWD(min) and tCPWDAtCPWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 7. Either tRCH or tRRH must be satisfied for a read cycle. 8. These parameters are referenced to the CAS falling edge in ealy write cycles and to the W falling edge in OE controlled write cycle and read-modify-write cycles. 9. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 10. These specifications are applied in the test mode. 11. In test mode read cycle, the values of tRAC, tAA and tCAC are delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet. 12. For all of the refresh modes except for distributed CAS -before- RAS refresh, 4096(4K Ref.)/2048(2K Ref.) cycles of burst refresh must be executed within 16ms before and after self-refresh in order to meet refresh specification.

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